1. Field of the Invention
Embodiments relate to the design of a memory controller.
2. Background
A memory controller is an interface between an external memory and a processing core, e.g., a central processing unit (CPU). A memory controller receives a memory access request from the CPU, which specifies the logical address of a data unit in the external memory. A “data unit” refers to smallest addressable unit of data in the memory, e.g., a byte, a word, or a double-word. The memory controller scrambles, or maps, the logical address bits into its physical address pins connecting to the memory.
As the memory controller typically has fewer physical address pins than the number of logical address bits, output from the physical address pins is time-multiplexed. In a typical synchronous dynamic random access memory (SDRAM) bus protocol, during a first time phase (which may take one or more clock periods) the memory controller delivers a row address. During a later time phase the memory controller delivers a column address. Typically, column address bits are the least-significant logical address bits received from the CPU. Bank address bits and row address bits are the more-significant logical address bits.
Different memories may have different sizes, e.g., row size, data width, or memory density. The term “data width” refers to the size of a data unit. The term “row size” refers to the number of bits in a row, which is equal to the data width multiplied by the number of columns. The term “memory density” refers to the total number of bits in the memory and is synonymous to “total memory size.” When the row size changes but data width remains the same, the number of columns changes. Thus, the number of column address bits changes and the positions of the row address bits are shifted to different positions in the logical address. As a result, when a memory controller is connected to a memory with a different row size, row address bits are routed onto different physical address pins. Similar changes occur when the data width of the memory varies.
Existing double data rate (DDR) SDRAM memory controllers handle limited row sizes for limited memory densities. The existing memory controllers are allowed to scramble many logical address bits arbitrarily as needed to simplify their design. However, the existing memory controllers cannot easily handle a wide range of memory sizes without greatly increasing their complexity.
Moreover, flash memory introduces new row sizes and may cause more scrambling scenarios to be built into the design of the memory controller. The variety of the scrambling scenarios would threaten to inflate the complexity of the memory controller's address output multiplexer. Due to the blocking and partitioning of memory cells in the flash memory, flash memory restricts address scrambling so that the memory controllers are prohibited from scrambling many logical address bits arbitrarily as was done in the past. The restriction thus eliminates one of the existing methods of simplifying the memory controller design.
To accommodate the different memory sizes, the address output multiplexer of the memory controller needs to be designed with configurable flexibility to increase the variability of memories with which the memory controller is compatible. The variability herein refers to dimensional parameters of the memory. The term “dimensional parameter” refers to the dimensions defining a memory including, but not limited to, row size, data width, and memory density. An increase in a memory dimension, e.g., row size, is usually associated with increased performance and increased cost. Part of the increase in cost comes from the increased complexity of the memory controller design. Thus, it is an objective of the circuit designer to accommodate a diverse range of memory dimensions without adding complexity to the address output multiplexers in the memory controller.